Monday, April 21, 2014

FUll Adder


This week we have to complete our assignment on the topic Adder , Full Adder.. Frankly speaking it is getting more harder now. Me myself trying to get in it.

This is the schematic circuit that I am drawing in the Gateway Silvaco Software. From here we have to run whether our circuit is function or not. This is what we called as simulation. Simulate in order to know the real analysis if the true circuit will be implemented.

So what is adder? What is mean by full adder? Where is it's application ?

In  electronics,  an adder or summer is a digital circuit   that performs addition of numbers. In many computers and other kinds of processors, adders are used not only in the arithmetic logic units,  but also in other parts of the processor, where they are used to calculate addresses, table indices, and similar operations.

Although adders can be constructed for many numerical representations, such as binary-coded decimal or excess-3, the most common adders operate on binary numbers. In cases where two's complement or ones' complement  is being used to represent negative numbers, it is trivial to modify an adder into an adder-subtractor. Other signed number representations require a more complex adder.


Full Adder


A full adder adds binary numbers and accounts for values carried in as well as out. A one-bit full adder adds three one-bit numbers, often written as A, B, and Cin; A and B are the operands, and Cin is a bit carried in from the next less significant stage. The full-adder is usually a component in a cascade of adders, which add 8, 16, 32, etc. bit binary numbers. The circuit produces a two-bit output, output carry and sum typically represented by the signals Cout and S, where \mathrm{sum} = 2 \times C_{out} + S. The one-bit full adder's truth table is:


A full adder can be implemented in many different ways such as with a custom transistor-level circuit or composed of other gates. One example implementation is with S = A \oplus B \oplus C_{in} and C_{out} = (A \cdot B) + (C_{in} \cdot (A \oplus B)).
In this implementation, the final OR gate before the carry-out output may be replaced by an XOR gate without altering the resulting logic. Using only two types of gates is convenient if the circuit is being implemented using simple IC chips which contain only one gate type per chip.

A full adder can be constructed from two half adders by connecting A and B to the input of one half adder, connecting the sum from that to an input to the second adder, connecting Ci to the other input and OR the two carry outputs. The critical path of a full adder runs through both XOR-gates and ends at the sum bit s. Assumed that an XOR-gate takes 3 delays to complete, the delay imposed by the critical path of a full adder is equal to
T_{FA} = 2 \cdot T_{XOR} = 2 \cdot 3 D = 6 D
The carry-block subcomponent consists of 2 gates and therefore has a delay of
T_c = 2 D

References: http://en.wikipedia.org/wiki/Adder_%28electronics%29

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